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CY7C63413 CY7C63513
Low-Speed High I/O, 1.5-Mbps USB Controller
1.0 Features 2.0 Functional Overview
* Low-cost solution for low-speed applications with high I/O requirements such as keyboards, keyboards with integrated pointing device, gamepads, and many others * USB Specification Compliance -- Conforms to USB Specification, Versions 1.1 and 2.0 -- Conforms to USB HID Specification, Version 1.1 -- Supports 1 device address and 3 data endpoints -- Integrated USB transceiver * 8-bit RISC microcontroller -- Harvard architecture -- 6-MHz external ceramic resonator -- 12-MHz internal CPU clock * Internal memory -- 256 bytes of RAM -- 8 Kbytes of EPROM (CY7C63413, CY7C63513) * Interface can auto-configure to operate as PS2 or USB * I/O port -- The CY763413/513 have 24 General Purpose I/O (GPIO) pins (Port 0 to 2) capable of sinking 7 mA per pin (typical) -- The CY7C63413/513 have eight GPIO pins (Port 3) capable of sinking 12 mA per pin (typical) which can drive LEDs -- Higher current drive is available by connecting multiple GPIO pins together to drive a common output -- Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs -- The CY7C63513 has an additional eight I/O pins on a DAC port which has programmable current sink outputs -- Maskable interrupts on all I/O pins * 12-bit free-running timer with one microsecond clock ticks * Watch Dog Timer (WDT) * Internal Power-On Reset (POR) * Improved output drivers to reduce EMI * Operating voltage from 4.0V to 5.5V DC * Operating temperature from 0 to 70 degrees Celsius * CY7C63413 available in 40-pin PDIP, 48-pin SSOP for production * CY7C63513 available in 48-pin SSOP packages for production * Industry-standard programmer support
The CY7C63413/513 are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C63413/513 features 32 General-Purpose I/O (GPIO) pins to support USB and other applications. The I/O pins are grouped into four ports (Port 0 to 3) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. The CY7C63413/513 have 24 GPIO pins (Ports 0 to 2) that are rated at 7 mA typical sink current. The CY7C63413/513 has 8 GPIO pins (Port 3) that are rated at 12 mA typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same "GPIO" interrupt vector. The CY7C63513 features an additional 8 I/O pins in the DAC port. Every DAC pin includes an integrated 14-Kohm pull-up resistor. When a "1" is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven high by the internal pull-up resistor. When a "0" is written to a DAC I/O pin, the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a "1" to the pin. The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits [1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits [7:2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Again, multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller and the interrupt polarity for each DAC I/O pin is individually programmable. The DAC port interrupts share a separate "DAC" interrupt vector. The Cypress microcontrollers use an external 6-MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller. The CY7C6413/513 are offered with single EPROM options. The CY7C63413 and CY7C63513 have 8 Kbytes of EPROM.
Cypress Semiconductor Corporation Document #: 38-08027 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised July 23, 2004
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These parts include Power-on Reset logic, a Watch Dog Timer, a vectored interrupt controller, and a 12-bit free-running timer. The Power-On Reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. The Watch Dog Timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the Watch Dog Timer periodically. If the Watch Dog Timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watch dog reset. The microcontroller supports eight maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-s and 1.024-ms outputs from the freerunning timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW "0" to HIGH "1." The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge ("0" to "1") or falling edge ("1" to "0"). The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128-s and 1.024-ms). The timer can be used to measure the duration of an event under firmware control by reading the timer twice: once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper four bits happened to increment right after the lower 8 bits are read. The CY7C63413/513 include an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. Finally, the CY7C63413/513 support PS/2 operation. With appropriate firmware the D+ and D- USB pins can also be used as PS/2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware.
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Pin Configuration Logic Block Diagram
6-MHz ceramic resonator CY7C63513 48-pin SSOP
D+ D- P3[7] P3[5] P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] DAC[7] DAC[5] P0[7] P0[5] P0[3] P0[1] DAC[3] DAC[1] VPP Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC Vss P3[6] P3[4] P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] DAC[6] DAC[4] P0[6] P0[4] P0[2] P0[0] DAC[2] DAC[0] XTALOUT XTALIN D+ D- P3[7] P3[5] P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC NC P0[7] P0[5] P0[3] P0[1] NC NC VPP Vss
CY7C63413 48-pin SSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC Vss P3[6] P3[4] P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] NC NC P0[6] P0[4] P0[2] P0[0] NC NC XTALOUT XTALIN
OSC
12 MHz 6 MHz
12-MHz 8-bit CPU
USB Transceiver
D+ USB PS/2 D- PORT
EPROM 4/6/8 Kbyte 8-bit Bus
USB SIE
RAM 256 byte
Interrupt Controller
P0[7]
P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] DAC[7] DAC[5] P0[7] P0[5]
D+ VCC Vss P3[6] P3[4]
P3[5] P3[7] D-
12-bit Timer
GPIO PORT 0
P0[0]
CY7C63413 48-Pad Die
D+
P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] DAC[6] DAC[4] P0[6] P0[4] Vss XTALIN XTALOUT DAC[0] DAC[2] P0[0] P0[2] P0[3] P0[1] DAC[3] DAC[1] VPP
CY7C63413 40-pin PDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC VSS P3[6] P3[4] P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] P0[6] P0[4] P0[2] P0[0] XTALOUT XTALIN
GPIO PORT 1
P1[0] P1[7]
GPIO PORT 2 Watch Dog Timer
P2[0] 0 P2[7]
GPIO PORT 3
P3[0] P3[7]
Power-on Reset
DAC PORT
DAC[0]
0
High Current Outputs
D- P3[7] P3[5] P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P0[7] P0[5] P0[3] P0[1] VPP Vss
TOP VIEW
DAC[7] CY7C63513 only
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3.0
Name D+, D- P0[7:0]
Pin Definitions
CY7C63413 I/O I/O I/O 40-Pin 1,2 48-Pin 1,2 Die 1,2 17,32,18, 31,19,30, 20,29 11,38,12, 37,13,36, 14,35 7,42,8, 41,9,40, 10,39 3,46,4,45, 5,44,6,43 15,34,16, 33,21,28, 22,27 25 26 23 48 24,47 CY7C63513 48-Pin 1,2 17,32,18, 31,19,30, 20,29 11,38,12, 37,13,36, 14,35 7,42,8, 41,9,40, 10,39 3,46,4, 45,5,44, 6,43 15,34,16, 33,21,28, 22,27 25 26 23 48 24,47 Description USB differential data; PS/2 clock and data signals GPIO port 0 capable of sinking 7 mA (typical)
15,26,16, 17,32,18, 25,17,24, 31,19,30, 18,23 20,29 11,30,12, 11,38,12, 29,13,28, 37,13,36, 14,27 14,35 7,34,8, 33,9,32, 10,31 3,38,4, 37,5,36, 6,35 n/a 7,42,8, 41,9,40, 10,39 3,46,4, 45,5,44, 6,43 n/a
P1[3:0]
I/O
GPIO Port 1 capable of sinking 7 mA (typical).
P2
I/O
GPIO Port 2 capable of sinking 7 mA (typical).
P3[7:4]
I/O
GPIO Port 3 capable of sinking 12 mA (typical).
DAC
I/O
DAC I/O Port with programmable current sink outputs. DAC[1:0] offer a programmable range of 3.2 to 16 mA typical. DAC[7:2] have a programmable sink current range of 0.2 to 1.0 mA typical. 6-MHz ceramic resonator or external clock input 6-MHz ceramic resonator Programming voltage supply, ground during operation Voltage supply Ground
XTALIN XTALOUT VPP VCC Vss
IN OUT
21 22 19 40 20,39
25 26 23 48 24,47
4.0
4.1
Programming Model
14-bit Program Counter (PC)
4.2
8-bit Accumulator (A)
The accumulator is the general purpose, do everything register in the architecture where results are usually calculated.
The 14-bit Program Counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C63413/513 architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This is typically a jump instruction to a reset handler that initializes the application. The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte "page" of sequential code should be an XPAGE instruction. The assembler directive "XPAGEON" will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution. The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction. Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.
4.3
8-bit Index Register (X)
The index register "X" is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.
4.4
8-bit Program Stack Pointer (PSP)
During a reset, the Program Stack Pointer (PSP) is set to zero. This means the program "stack" starts at RAM address 0x00 and "grows" upward from there. Note the program stack pointer is directly addressable under firmware control, using the MOV PSP instruction. The PSP supports interrupt service ,A under hardware control and CALL, RET, and RETI instructions under firmware control. During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented. The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program "stack" and increment the program stack pointer by two. The Return From Interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP The program stack pointer is . Page 4 of 31
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decremented again and the first byte is restored from memory addressed by the PSP After the program counter and flags . have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts. The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two. The Return From Subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two. This instruction will require two bytes of code where the first byte identifies the "MOV A" instruction with a data operand as the second byte. The second byte of the instruction will be the constant "0xE8". A constant may be referred to by name if a prior "EQU" statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above: * DSPINIT: EQU 0E8h * MOV A,DSPINIT 4.6.2 Direct
4.5
8-bit Data Stack Pointer (DSP)
The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP then write data , to the memory location addressed by the DSP A POP instruc. tion will read data from the memory location addressed by the DSP then post-increment the DSP , . During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem. For USB applications, it is strongly recommended that the DSP is loaded after reset just below the USB DMA buffers.
"Direct" address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10: * MOV A, [10h] In normal usage, variable names are assigned to variable addresses using "EQU" statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above: * buttons: EQU 10h * MOV A,[buttons] 4.6.3 Indexed
4.6
Address Modes
The CY7C63413/513 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 4.6.1 Data
The "Data" address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xE8: * MOV A,0E8h
"Indexed" address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the "X" register. In normal usage, the constant will be the "base" address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed: * array: EQU 10h * MOV X,3 * MOV A,[x+array] This would have the effect of loading A with the fourth element of the SRAM "array" that begins at address 0x10. The fourth element would be at address 0x13.
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5.0
HALT ADD A,expr ADD A,[expr] ADD A,[X+expr] ADC A,expr ADC A,[expr] ADC A,[X+expr] SUB A,expr SUB A,[expr] SUB A,[X+expr] SBB A,expr SBB A,[expr] SBB A,[X+expr] OR A,expr OR A,[expr] OR A,[X+expr] AND A,expr AND A,[expr] AND A,[X+expr] XOR A,expr XOR A,[expr] XOR A,[X+expr] CMP A,expr CMP A,[expr] CMP A,[X+expr] MOV A,expr MOV A,[expr] MOV A,[X+expr] MOV X,expr MOV X,[expr] reserved XPAGE MOV A,X MOV X,A MOV PSP ,A CALL JMP CALL JZ JNZ addr addr addr addr addr data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct
Instruction Set Summary
MNEMONIC operand opcode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 40 41 60 50-5F 80-8F 90-9F A0-AF B0-BF 4 4 4 4 10 5 10 5 5 JC JNC JACC INDEX addr addr addr addr C0-CF D0-DF E0-EF F0-FF 5 5 7 14 cycles 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 5 7 8 4 5 6 4 5 NOP INC A INC X INC [expr] INC [X+expr] DEC A DEC X DEC [expr] DEC [X+expr] IORD expr IOWR expr POP A POP X PUSH A PUSH X SWAP A,X SWAP A,DSP MOV [expr],A MOV [X+expr],A OR [expr],A OR [X+expr],A AND [expr],A AND [X+expr],A XOR [expr],A XOR [X+expr],A IOWX [X+expr] CPL ASL ASR RLC RRC RET DI EI RETI direct index direct index direct index direct index index acc x direct index acc x direct index address address MNEMONIC operand opcode 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 70 72 73 4 4 4 7 8 4 4 7 8 5 5 4 4 5 5 5 5 5 6 7 8 7 8 7 8 6 4 4 4 4 4 8 4 4 8 cycles
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6.0
6.1
Memory Organization
Program Memory Organization
after reset 14-bit PC Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A Program execution begins here after a reset USB Bus Reset interrupt vector 128-s timer interrupt vector 1.024-ms timer interrupt vector USB address A endpoint 0 interrupt vector USB address A endpoint 1 interrupt vector USB address A endpoint 2 interrupt vector Reserved Reserved Reserved DAC interrupt vector GPIO interrupt vector Reserved Program Memory begins here
0x1FDF
(8K - 32 bytes) 8-KB PROM ends here (CY7C63413, CY7C63513)
Figure 6-1. Program Memory Space with Interrupt Vector Table
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6.2 Data Memory Organization
areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:
The CY7C63413/513 microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four after reset Address Program Stack begins here and grows upward 8-bit PSP 0x00 8-bit DSP user
Data Stack begins here and grows downward The user determines the amount of memory required
User Variables
0xE8 USB FIFO for Address A endpoint 2 0xF0 USB FIFO for Address A endpoint 1 0xF8 USB FIFO for Address A endpoint 0 Top of RAM Memory 0xFF
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6.3 I/O Register Summary
lator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumuTable 6-1. I/O Register Summary Register Name Port 0 Data Port 1 Data Port 2 Data Port 3 Data Port 0 Interrupt Enable Port 1 Interrupt Enable Port 2 Interrupt Enable Port 3 Interrupt Enable GPIO Configuration USB Device Address A EP A0 Counter Register EP A0 Mode Register EP A1 Counter Register EP A1 Mode Register EP A2 Counter Register EP A2 Mode Register USB Status & Control Global Interrupt Enable Endpoint Interrupt Enable Timer (LSB) Timer (MSB) WDR Clear DAC Data DAC Interrupt Enable DAC Interrupt Polarity DAC Isink Processor Status & Control I/O Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x1F 0x20 0x21 0x24 0x25 0x26 0x30 0x31 0x32 0x38-0x3F 0xFF
Read/Write R/W R/W R/W R/W W W W W R/W R/W R/W R/W R/W R/C R/W R/C R/W R/W R/W R R W R/W W W W R/W GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3
Function
Interrupt enable for pins in Port 0 Interrupt enable for pins in Port 1 Interrupt enable for pins in Port 2 Interrupt enable for pins in Port 3 GPIO Ports Configurations USB Device Address A USB Address A, Endpoint 0 counter register USB Address A, Endpoint 0 configuration register USB Address A, Endpoint 1 counter register USB Address A, Endpoint 1 configuration register USB Address A, Endpoint 2 counter register USB Address A, Endpoint 2 configuration register USB upstream port traffic status and control register Global interrupt enable register USB endpoint interrupt enables Lower eight bits of free-running timer (1 MHz) Upper four bits of free-running timer that are latched when the lower eight bits are read. Watch Dog Reset clear DAC I/O Interrupt enable for each DAC pin Interrupt polarity for each DAC pin One four bit sink current register for each DAC pin Microprocessor status and control
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7.0 Clocking
Clock Distribution clk1x (to USB SIE) clk2x (to Microcontroller) Clock Doubler 30 pF 30 pF XTALOUT
XTALIN
Figure 7-1. Clock Oscillator On-chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect a low-cost ceramic resonator or an external oscillator can be connected to these pins to provide a reference frequency for the internal clock distribution and clock doubler. An external 6 MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Please note that grounding the XTALOUT pin is not permissible as the internal clock is effectively shorted to ground. the "main" loop of code. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results.
8.1
Power-On Reset (POR)
8.0
Reset
The USB Controller supports three types of resets. All registers are restored to their default states during a reset. The USB Device Addresses are set to 0 and all interrupts are disabled. In addition, the Program Stack Pointer (PSP) and Data Stack Pointer (DSP) are set to 0x00. For USB applications, the firmware should set the DSP below 0xE8 to avoid a memory conflict with RAM dedicated to USB FIFOs. The assembly instructions to do this are shown below: Mov A, E8h Swap A,dsp ; Move 0xE8 hex into Accumulator ; Swap accumulator value into dsp register
Power-On Reset (POR) occurs every time the V CC voltage to the device ramps from 0V to an internally defined trip voltage (Vrst) of approximately 1/2 full supply voltage. In addition to the normal reset initialization noted under "Reset," bit 4 (PORS) of the Processor Status and Control Register is set to "1" to indicate to the firmware that a Power-On Reset occurred. The POR event forces the GPIO ports into input mode (high impedance), and the state of Port 3 bit 7 is used to control how the part will respond after the POR releases. If Port 3 bit 7 is HIGH (pulled to V CC) and the USB IO are at the idle state (DM HIGH and DP LOW) the part will go into a semi-permanent power down/suspend mode, waiting for the USB IO to go to one of Bus Reset, K (resume) or SE0. If Port 3 bit 7 is still HIGH when the part comes out of suspend, then a 128-s timer starts, delaying CPU operation until the ceramic resonator has stabilized. If Port 3 bit 7 was LOW (pulled to VSS) the part will start a 96ms timer, delaying CPU operation until VCC has stabilized, then continuing to run as reset. Firmware should clear the POR Status (PORS) bit in register 0xFF before going into suspend as this status bit selects the 128-s or 96-ms start-up timer value as follows: IF Port 3 bit 7 is HIGH then 128-s is always used; ELSE if PORS is HIGH then 96-ms is used; ELSE 128-s is used.
The three reset types are: 1. Power-On Reset (POR) 2. Watch Dog Reset (WDR) 3. USB Bus Reset (non hardware reset) The occurrence of a reset is recorded in the Processor Status and Control Register located at I/O address 0xFF. Bits 4, 5, and 6 are used to record the occurrence of POR, USB Reset, and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset. The microcontroller begins execution from ROM address 0x0000 after a POR or WDR reset. Although this looks like interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. That means the reset handler in firmware should initialize the hardware and begin executing
8.2
Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal reset initialization noted under "Reset," bit 6 of the Processor Status and Control Register is set to "1" to indicate to the firmware that a Watch Dog Reset occurred.
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8.192 ms to 14.336 ms
2.048 ms
At least 8.192 ms since last write to WDT
WDR goes high for 2.048 ms
Execution begins at Reset Vector 0X00
Figure 8-1. Watch Dog Reset (WDR) The Watch Dog Timer is a 2-bit timer clocked by a 4.096-ms clock (bit 11) from the free-running timer. Writing any value to the write-only Watch Dog Clear I/O port (0x26) will clear the Watch Dog Timer. In some applications, the Watch Dog Timer may be cleared in the 1.024-ms timer interrupt service routine. If the 1.024-ms timer interrupt service routine does not get executed for 8.192 ms or more, a Watch Dog Timer Reset will occur. A Watch Dog Timer Reset lasts for 2.048 ms after which the microcontroller begins execution at ROM address 0x0000. The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The USB transmitter remains disabled until the MSB of the USB address register is set.
9.0
General Purpose I/O Ports
VCC
mode 2 bits Data Out Latch Q1 Control Q3
GPIO CFG
Internal Data Bus
7 k
Port Write Q2 ESD Internal Buffer
GPIO Pin
Control
Port Read Interrupt Enable
to Interrupt Controller
Figure 9-1. Block Diagram of a GPIO Line Ports 0 to 2 provide 24 GPIO pins that can be read or written. Each port (8 bits) can be configured as inputs with internal pullups, open drain outputs, or traditional CMOS outputs. Please note an open drain output is also a high-impedance (no pullup) input. All of the I/O pins within a given port have the same configuration. Ports 0 to 2 are considered low current drive with typical current sink capability of 7 mA. The internal pull-up resistors are typically 7 k. Two factors govern the enabling and disabling of the internal pull-up resistors: the port configuration selected in the GPIO Configuration register and the state of the output data bit. If the GPIO Configuration selected is "Resistive" and the output data bit is "1," then the internal pull-up resistor is enabled for that GPIO pin. Otherwise, Q1 is turned off and the 7-k pull-up is disabled. Q2 is "ON" to sink current whenever the output data bit is written as a "0." Q3 provides "HIGH" source current when the GPIO port is configured for CMOS outputs and the output data bit is written as a "1". Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of current to support traditional CMOS outputs with symmetric drive
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.
Addr: 0x00 P0[7] R/W P0[6] R/W P0[5] R/W
Port 0 Data P0[4] R/W P0[3] R/W P0[2] R/W P0[1] R/W P0[0] R/W
Table 9-1. Port 0 Data Addr: 0x01 P1[7] R/W P1[6] R/W P1[5] R/W Port 1 Data P1[4] R/W P1[3] R/W P1[2] R/W P1[1] R/W P1[0] R/W
Table 9-2. Port 1 Data Addr: 0x02 P2[7] R/W P2[6] R/W P2[5] R/W Port 2 Data P2[4] R/W P2[3] R/W P2[2] R/W P2[1] R/W P2[0] R/W
Table 9-3. Port 2 Data Addr: 0x03 P3[7] R/W P3[6] R/W P3[5] R/W Port 3 Data P3[4] R/W P3[3] R/W P3[2] R/W P3[1] R/W P3[0] R/W
Table 9-4. Port 3 Data Addr: 0x30 DAC Port Data Low current outputs 0.2 mA to 1.0 mA typical DAC[7] R/W DAC[6] R/W DAC[5] R/W DAC[4] R/W DAC[3] R/W DAC[2] R/W High current outputs 3.2 mA to 16 mA typical DAC[1] R/W DAC[0] R/W
Table 9-5. DAC Port Data Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. An open drain output is also a high-impedance input. Port 3 offers high current drive with a typical current sink capability of 12 mA. The internal pull-up resistors are typically 7 k. Note: Special care should be exercised with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB Specification. If a `1' is written to the unused data bit and the port is configured with open drain outputs, the unused data bit will be in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a `0.' During reset, all of the bits in the GPIO to a default configuration of Open Drain output, positive interrupt polarity for all GPIO ports.
9.1
GPIO Interrupt Enable Ports
During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a "1" to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin.
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Addr: 0x04 P0[7] W P0[6] W P0[5] W Port 0 Interrupt Enable P0[4] W P0[3] W P0[2] W P0[1] W P0[0] W
Table 9-6. Port 0 Interrupt Enable Addr: 0x05 P1[7] W P1[6] W P1[5] W Port 1 Interrupt Enable P1[4] W P1[3] W P1[2] W P1[1] W P1[0] W
Table 9-7. Port 1 Interrupt Enable Addr: 0x06 P2[7] W P2[6] W P2[5] W Port 2 Interrupt Enable P2[4] W P2[3] W P2[2] W P2[1] W P2[0] W
Table 9-8. Port 2 Interrupt Enable Addr: 0x07 P3[7] W P3[6] W P3[5] W Port 3 Interrupt Enable P3[4] W P3[3] W P3[2] W P3[1] W P3[0] W
Table 9-9. Port 3 Interrupt Enable
9.2
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In addition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising edge ("0" to Port Configuration bits 11 10 10 01 00 Pin Interrupt Bit X 0 1 X X
"1") on an input pin causes an interrupt. With negative polarity, a falling edge ("1" to "0") on an input pin causes an interrupt. As shown in the table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. The GPIO Configuration Port register provides two bits per port to program these features. The possible port configurations are: Driver Mode Resistive CMOS Output Open Drain Open Drain Open Drain Interrupt Polarity disabled disabled + (default)
In "Resistive" mode, a 7-k pull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled for any pin that has been written as a "1." The resistor is disabled on any pin that has been written as a "0." An I/O pin will be driven high through a 7-k pull-up resistor when a "1" has been written to the pin. Or the output pin will be driven LOW, with the pull-up disabled, when a "0" has been written to the pin. An I/O pin that has been written as a "1" can be used as an input pin with an integrated 7-k pull-up resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the GPIO interrupt enabled. In "CMOS" mode, all pins of the GPIO port are outputs that are actively driven. The current source and sink capacity are roughly the same (symmetric output drive). A CMOS port is not a possible source for interrupts. A port configured in CMOS mode has interrupt generation disabled, yet the interrupt mask bits serve to control port direction.
If a port's associated Interrupt Mask bits are cleared, those port bits are strictly outputs. If the Interrupt Mask bits are set then those bits will be open drain inputs. As open drain inputs, if their data output values are `1' those port pins will be CMOS inputs (HIGH Z output). In "Open Drain" mode the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An I/O pin that has been written as a "1" can be used as either a high-impedance input or a three-state output. An I/O pin that has been written as a "0" will drive the output LOW. The interrupt polarity for an open drain GPIO port can be selected as either positive (rising edge) or negative (falling edge). During reset, all of the bits in the GPIO Configuration Register are written with "0." This selects the default configuration: Open Drain output, positive interrupt polarity for all GPIO ports.
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Addr: 0x08 7 Port 3 Config Bit 1 W 6 Port 3 Config Bit 0 W 5 Port 2 Config Bit 1 W GPIO Configuration Register 4 Port 2 Config Bit 0 W 3 Port 1 Config Bit 1 W 2 Port 1 Config Bit 0 W 1 Port 0 Config Bit 1 W 0 Port 0 Config Bit 0 W
Table 9-10. GPIO Configuration Register
10.0
DAC Port
VCC
Data Out Latch Q1
Internal Data Bus
14 K DAC Write Isink Register Internal Buffer 4 bits Isink DAC
DAC I/O Pin
ESD
DAC Read Interrupt Enable Interrupt Polarity Interrupt Logic
to Interrupt Controller
Figure 10-1. Block Diagram of DAC Port The DAC port provides the CY7C63513 with 8 programmable current sink I/O pins. Writing a "1" to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O pin HIGH through an integrated 14 Kohm resistor. When a "0" is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up resistor is disabled. A "0" output will cause the Isink DAC to sink current to drive the output LOW. The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register for that output pin. DAC[1:0] are the two high current outputs that are programAddr: 0x30 mable from a minimum of 3.2 mA to a maximum of 16 mA (typical). DAC[7:2] are low current outputs that are programmable from a minimum of 0.2 mA to a maximum of 1.0 mA (typical). When a DAC I/O bit is written as a "1," the I/O pin is either an output pulled high through the 14 Kohm resistor or an input with an internal 14 Kohm pull-up resistor. All DAC port data bits are set to "1" during reset.
DAC Port Data Low current outputs 0.2 mA to 1.0 mA typical High current outputs 3.2 mA to 16 mA typical DAC[3] R/W DAC[2] R/W DAC[1] R/W DAC[0] R/W
DAC[7] R/W
DAC[6] R/W
DAC[5] R/W
DAC[4] R/W
Table 10-1. DAC Port Data
10.1
DAC Port Interrupts
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this feature with an interrupt mask bit for each DAC I/O pin. Writing a "1" to a bit in this register enables interrupts from the corre-
sponding bit position. Writing a "0" to a bit in the DAC Port Interrupt Enable register disables interrupts from the corresponding bit position. All of the DAC Port Interrupt Enable register bits are cleared to "0" during a reset.
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Addr: 0x31 DAC[7] W DAC[6] W DAC[5] W DAC Port Interrupt Enable DAC[4] W DAC[3] W DAC[2] W DAC[1] W DAC[0] W
Table 10-2. DAC Port Interrupt Enable As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register. Writing a "0" to a bit selects negative polarity (falling edge) that will cause an interrupt (if enabled) if a falling edge transition occurs on the corresponding input pin. Writing a "1" to a bit in Addr: 0x32 DAC[7] W DAC[6] W DAC[5] W this register selects positive polarity (rising edge) that will cause an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are cleared during a reset.
DAC Port Interrupt Polarity DAC[4] W DAC[3] W DAC[2] W DAC[1] W DAC[0] W
Table 10-3. DAC Port Interrupt Polarity
10.2
DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven Addr: 0x38-0x3F Reserved
LOW. The first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F controls the current to DAC[7].
DAC Port Interrupt Polarity Isink Value Isink[3] W Table 10-4. DAC Port Isink Isink[2] W Isink[1] W Isink[0] W
11.0
USB Serial Interface Engine (SIE)
11.1
USB Enumeration
The SIE allows the microcontroller to communicate with the USB host. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller: * Bit stuffing/unstuffing * Checksum generation/checking * ACK/NAK * Token type identification * Address checking Firmware is required to handle the rest of the USB interface with the following tasks: * Coordinate enumeration by responding to set-up packets * Fill and empty the FIFOs * Suspend/Resume coordination * Verify and select Data toggle values
The enumeration sequence is shown below: 1. The host computer sends a Setup packet followed by a Data packet to USB address 0 requesting the Device descriptor. 2. The USB Controller decodes the request and retrieves its Device descriptor from the program memory space. 3. The host computer performs a control read sequence and the USB Controller responds by sending the Device descriptor over the USB bus. 4. After receiving the descriptor, the host computer sends a Setup packet followed by a Data packet to address 0 assigning a new USB address to the device. 5. The USB Controller stores the new address in its USB Device Address Register after the no-data control sequence is complete. 6. The host sends a request for the Device descriptor using the new USB address. 7. The USB Controller decodes the request and retrieves the Device descriptor from the program memory. 8. The host performs a control read sequence and the USB Controller responds by sending its Device descriptor over the USB bus. 9. The host generates control reads to the USB Controller to request the Configuration and Report descriptors. 10.The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB.
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11.2 PS/2 Operation
Bits [2:0] defaults to `000' at reset which allows the USB SIE to control output on D+ and D-. Firmware can override the SIE and directly control the state of these pins via these 3 control bits. Since PS/2 is an open drain signaling protocol, these modes allow all 4 PS/2 states to be generated on the D+ and D- pins
PS/2 operation is possible with the CY7C63413/513 series through the use of firmware and several operating modes. The first enabling feature: 1. USB Bus reset on D+ and D- is an interrupt that can be disabled; 2. USB traffic can be disabled via bit 7 of the USB register; 3. D+ and D- can be monitored and driven via firmware as independent port bits. Bits 5 and 4 of the Upstream Status and Control register are directly connected to the D+ and D- USB pins of the CY7C63413/513. These pins constantly monitor the levels of these signals with CMOS input thresholds. Firmware can poll and decode these signals as PS/2 clock and data. Addr:0x1F 7 Reserved 6 Reserved 5 D+ R
11.3
USB Port Status and Control
USB status and control is regulated by the USB Status and Control Register located at I/O address 0x1F as shown in Figure 11-1. This is a read/write register. All reserved bits must be written to zero. All bits in the register are cleared during reset.
USB Status and Control Register 4 D- R 3 Bus Activity R/W 2 Control Bit 2 R/W 1 Control Bit 1 R/W 0 Control Bit 0 R/W
Table 11-1. USB Status and Control Register The Bus Activity bit is a "sticky" bit that indicates if any non-idle USB event has occurred on the USB bus. The user firmware should check and clear this bit periodically to detect any loss of bus activity. Writing a "0" to the Bus Activity bit clears it while writing a "1" preserves the current value. In other words, the Control Bits 000 001 010 011 100 101 110 111 firmware can clear the Bus Activity bit, but only the SIE can set it. The 1.024-ms timer interrupt service routine is normally used to check and clear the Bus Activity bit. The following table shows how the control bits are encoded for this register.
Control Action Not forcing (SIE controls driver) Force K (D+ HIGH, D- LOW) Force J (D+ LOW, D- HIGH) Force SE0 (D+ LOW, D- LOW) Force SE0 (D- LOW, D+ LOW) Force D- LOW, D+ HiZ Force D- HiZ, D+ LOW Force D- HiZ, D+ HiZ
12.0
USB Device
12.1
USB Ports
USB Device Address A includes three endpoints: EPA0, EPA1, and EPA2. End Point 0 (EPA0) allows the USB host to recognize, set up, and control the device. In particular, EPA0 is used to receive and transmit control (including set-up) packets. Addr:0x10 Device Address Enable R/W Device Address Bit 6 R/W Device Address Bit 5 R/W
The USB Controller provides one USB device address with three endpoints. The USB Device Address Register contents are cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 12-1 shows the format of the USB Address Register.
USB Device Address Register Device Address Bit 4 R/W Device Address Bit 3 R/W Device Address Bit 2 R/W Device Address Bit 1 R/W Device Address Bit 0 R/W
Table 12-1. USB Device Address Register
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Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the serial interface engine (SIE) will respond to USB traffic to this address. The Device Address in bits [6:0] must be set by firmware during the USB enumeration process to an address assigned by the USB host that does not equal zero. This register is cleared by a hardware reset or the USB bus reset. mented as 8 bytes of dedicated SRAM. There are three endpoints defined for Device "A" that are labeled "EPA0," "EPA1," and EPA2." All USB devices are required to have an endpoint number 0 (EPA0) that is used to initialize and control the USB device. End Point 0 provides access to the device configuration information and allows generic USB status and control accesses. End Point 0 is bidirectional as the USB controller can both receive and transmit data. The endpoint mode registers are cleared during reset. The EPA0 endpoint mode register uses the format shown below:
12.2
Device Endpoints (3)
The USB controller communicates with the host using dedicated FIFOs, one per endpoint. Each endpoint FIFO is impleAddr:0x12 Endpoint 0 Set-up Received R/W Endpoint 0 In Received R/W Endpoint 0 Out Received R/W
USB Device EPA0, Mode Register Acknowledge Mode Bit 3 R/W Mode Bit 2 R/W Mode Bit 1 R/W Mode Bit 0 R/W
R/W
Table 12-2. USB Device EPA0, Mode Register Bits[7:5] in the endpoint 0 mode registers (EPA0) are "sticky" status bits that are set by the SIE to report the type of token that was most recently received. The sticky bits must be cleared by firmware as part of the USB processing. Addr: 0x14, 0x16 Reserved R/W Reserved R/W The endpoint mode registers for EPA1 and EPA2 do not use bits [7:5] as shown below:
USB Device Endpoint Mode Register Reserved R/W Acknowledge R/W Mode Bit 3 R/W Mode Bit 2 R/W Mode Bit 1 R/W Mode Bit 0 R/W
Table 12-3. USB Device Endpoint Mode Register The `Acknowledge' bit is set whenever the SIE engages in a transaction that completes with an `ACK' packet. The `set-up' PID status (bit[7]) is forced HIGH from the start of the data packet phase of the set-up transaction, until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently until the CPU first does an IORD to this endpoint 0 mode register. Bits[6:0] of the endpoint 0 mode register are locked from CPU IOWR operations only if the SIE has updated one of these bits, which the SIE does only at the end of a packet transaction (setup... Data... ACK, or Out... Data... ACK, or In... Data... ACK). The CPU can unlock these bits by doing a subsequent I/O read of this register. Addr: 0x11, 0x13, 0x15 Data 0/1 Toggle R/W Data Valid R/W Reserved R/W Firmware must do an IORD after an IOWR to an endpoint 0 register to verify that the contents have changed and that the SIE has not updated these values. While the `set-up' bit is set, the CPU cannot write to the DMA buffers at memory locations 0xE0 through 0xE7 and 0xF8 through 0xFF. This prevents an incoming set-up transaction from conflicting with a previous In data buffer filling operation by firmware. The mode bits (bits [3:0]) in an Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Section 16.0. The format of the endpoint Device counter registers is shown below:
USB Device Counter Registers Reserved R/W Byte count Bit 3 R/W Byte count Bit 2 R/W Byte count Bit 1 R/W Byte count Bit 0 R/W
Table 12-4. USB Device Counter Registers Bits 0 to 3 indicate the number of data bytes to be transmitted during an IN packet, valid values are 0 to 8 inclusive. Data Valid bit 6 is used for OUT and set-up tokens only. Data 0/1 Toggle bit 7 selects the DATA packet's toggle state: 0 for DATA0, 1 for DATA1.
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13.0 12-bit Free-running Timer
upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is actually reading the count stored in the temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time.
The 12-bit timer provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the
13.1
Timer (LSB)
Addr: 0x24 Timer Bit 7 R Timer Bit 6 R Timer Bit 5 R Timer Register (LSB) Timer Bit 4 R Timer Bit 3 R Timer Bit 2 R Timer Bit 1 R Timer Bit 0 R
Table 13-1. Timer Register
13.2
Timer (MSB)
Addr: 0x25 Timer Register (MSB) Reserved Reserved Timer Bit 11 R Table 13-2. Timer Register Timer Bit 10 R Timer Bit 9 R Timer Bit 8 R
Reserved
Reserved
1.024-ms interrupt 128-s interrupt
11
10
9
8
7
6
5
4
3
2
1
0
1-MHz clock
L3
L2
L1
L0
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0 To Timer Register
8
Figure 13-1. Timer Block Diagram
14.0
Processor Status and Control Register
Addr: 0xFF 7 6 Watch Dog Reset R/W 5 USB Bus Reset R/W Processor Status and Control Register 4 Power-on Reset R/W 3 Suspend, Wait for Interrupt R/W 2 Interrupt Mask R POR Default: 0x0101 WDC Reset: 0x41 1 Single Step R/W 0 Run R/W
IRQ Pending R
Table 14-1. Processor Status and Control Register The "Run" (bit 0) is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at Document #: 38-08027 Rev. *A the end of the current instruction. The processor remains halted until a reset (Power On or Watch Dog). Notice, when writing Page 18 of 31
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to the processor status and control register, the run bit should always be written as a "1." The "Single Step" (bit 1) is provided to support a hardware debugger. When single step is set, the processor will execute one instruction and halt (clear the run bit). This bit must be cleared for normal operation. The "Interrupt Mask" (bit 2) shows whether interrupts are enabled or disabled. The firmware has no direct control over this bit as writing a zero or one to this bit position will have no effect on interrupts. Instructions DI, EI, and RETI manipulate the internal hardware that controls the state of the interrupt mask bit in the Processor Status and Control Register. Writing a "1" to "Suspend, Wait for Interrupts" (bit 3) will halt the processor and cause the microcontroller to enter the "suspend" mode that significantly reduces power consumption. A pending interrupt or bus activity will cause the device to come out of suspend. After coming out of suspend, the device will resume firmware execution at the instruction following the IOWR which put the part into suspend. An IOWR that attempts to put the part into suspend will be ignored if either bus activity or an interrupt is pending. The "Power-on Reset" (bit 4) is only set to "1" during a power on reset. The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a Power On condition or a Watch Dog Timeout. PORS is used to determine suspend start-up timer value of 128 s or 96 ms. The "USB Bus Reset" (bit 5) will occur when a USB bus reset is received. The USB Bus Reset is a singled-ended zero (SE0) that lasts more than 8 microseconds. An SE0 is defined as the condition in which both the D+ line and the D- line are LOW Addr: 0x20 7 Reserved 6 Reserved 5 GPIO Interrupt Enable R/W at the same time. When the SIE detects this condition, the USB Bus Reset bit is set in the Processor Status and Control register and an USB Bus Reset interrupt is generated. Please note this is an interrupt to the microcontroller and does not actually reset the processor. The "Watch Dog Reset" (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went for more than 8 ms between watch dog clears. The "IRQ Pending" (bit 7) indicates one or more of the interrupts has been recognized as active. The interrupt acknowledge sequence should clear this bit until the next interrupt is detected. During Power-on Reset, the Processor Status and Control Register is set to 00010001, which indicates a Power-on Reset (bit 4 set) has occurred and no interrupts are pending (bit 7 clear) yet. During a Watch Dog Reset, the Processor Status and Control Register is set to 01000001, which indicates a Watch Dog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear) yet.
15.0
Interrupts
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a "1" to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts.
Global Interrupt Enable Register 4 DAC Interrupt Enable R/W 3 Reserved 2 1.024-ms Interrupt Enable R/W 1 128-sec Interrupt Enable R/W 0 USB Bus RST Interrupt Enable R/W
Table 15-1. Global Interrupt Enable Register
Addr: 0x21 7 Reserved 6 Reserved 5
USB End Point Interrupt Enable Register 4 Reserved 3 Reserved 2 EPA2 Interrupt Enable R/W Table 15-2. USB End Point Interrupt Enable Register 1 EPA1 Interrupt Enable R/W 0 EPA0 Interrupt Enable R/W Reserved
Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the hardware will first disable all interrupts by clearing the Interrupt Enable bit in the Processor Status and Control Register. Next, the interrupt latch of the current interrupt is cleared. This is followed by a CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt Vector). The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service Document #: 38-08027 Rev. *A
routine by executing an EI instruction. Interrupts can be nested to a level limited only by the available stack space. The Program Counter value as well as the Carry and Zero flags (CF, ZF) are automatically stored onto the Program Stack by the CALL instruction as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the processor state is preserved and restored during an interrupt. The PUSH A instruction should be used as the first command in the ISR to save the accumulator value and the POP A inPage 19 of 31
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struction should be used just before the RETI instruction to restore the accumulator value. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed.
15.1
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 15-1. Although Reset is not an interrupt, per se, the first instruction executed after a reset is at PROM address 0x0000--which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.
Table 15-3. Interrupt Vector Assignments Interrupt Vector Number not applicable 1 2 3 4 5 6 7 8 9 10 11 12 ROM Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 15.2.3 Function Execution after Reset begins here USB Bus Reset interrupt 128-s timer interrupt 1.024-ms timer interrupt USB Address A Endpoint 0 interrupt USB Address A Endpoint 1 interrupt USB Address A Endpoint 2 interrupt Reserved Reserved Reserved DAC interrupt GPIO interrupt Reserved USB Endpoint Interrupts
15.2
Interrupt Latency
Interrupt latency can be calculated from the following equation: Interrupt Latency =(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for the JMP instruction) For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the Interrupt Service Routine will execute a min. of 16 clocks (1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is issued. Remember that the interrupt latches are sampled at the rising edge of the last clock cycle in the current instruction. 15.2.1 USB Bus Reset Interrupt
There are three USB endpoint interrupts, one per endpoint. The USB endpoints interrupt after the either the USB host or the USB controller sends a packet to the USB. 15.2.4 DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled.The interrupt polarity for each DAC I/O pin is programmable. A positive polarity is a rising edge input while a negative polarity is a falling edge input. All of the DAC pins share a single interrupt vector, which means the firmware will need to read the DAC port to determine which pin or pins caused an interrupt. Please note that if one DAC pin triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive (non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process. 15.2.5 GPIO Interrupt
The USB Bus Reset interrupt is asserted when a USB bus reset condition is detected. A USB bus reset is indicated by a single ended zero (SE0) on the upstream port for more than 8 microseconds. 15.2.2 Timer Interrupt
There are two timer interrupts: the 128-s interrupt and the 1.024-ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the interrupts first or the suspend request first.
Each of the 32 GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware will need to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. Please note that if one port pin triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive (non-trigger) state or its corresponding
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port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
16.0
Mode Disable
Truth Tables
Encoding 0000 0001 Setup ignore accept 0010 0011 0100 0101 accept accept accept ignore 0110 0111 accept ignore 1000 1001 1010 1011 1100 1101 1110 1111 ignore ignore accept accept ignore ignore accept accept In ignore NAK stall stall ignore ignore TX 0 TX cnt ignore ignore TX 0 TX 0 NAK TX cnt NAK TX cnt Out ignore NAK check stall ignore always stall ignore NAK ACK NAK ACK ignore ignore check Check Comments Ignore all USB traffic to this endpoint Forced from Set-up on Control endpoint, from modes other than 0000 For Control endpoints For Control endpoints For Control endpoints Available to low speed devices, future USB spec enhancements For Control Endpoints Available to low speed devices, future USB spec enhancements An ACK from mode 1001 --> 1000 This mode is changed by SIE on issuance of ACK --> 1000 An ACK from mode 1011 --> 1010 This mode is changed by SIE on issuance of ACK --> 1010 An ACK from mode 1101 --> 1100 This mode is changed by SIE on issuance of ACK --> 1100 An ACK from mode 1111 --> 1110 NAck In - Status Out This mode is changed by SIE on issuance of ACK -->1110
Table 16-1. USB Register Mode Encoding
Nak In/Out Status Out Only Stall In/Out Ignore In/Out Isochronous Out Status In Only Isochronous In Nak Out Ack Out Nak Out - Status In Ack Out - Status In Nak In Ack In Nak In - Status Out Ack In - Status Out
The `In' column represents the SIE's response to the token type. A disabled endpoint will remain such until firmware changes it, and all endpoints reset to disabled. Any Setup packet to an enabled and accepting endpoint will be changed by the SIE to 0001 (NAKing). Any mode which indicates the acceptance of a Setup will acknowledge it. Most modes that control transactions involving an ending ACK will be changed by the SIE to a corresponding mode which NAKs follow on packets. A Control endpoint has three extra status bits for PID (Setup, In and Out), but must be placed in the correct mode to function as such. Also a non-Control endpoint can be made to act as a Control endpoint if it is placed in a non appropriate mode. A `check' on an Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG) of 1.
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Figure 16-1. Decode table forTable 16-2: "Details of Modes for Differing Traffic Conditions" Properties of incoming packet Encoding Status bits What the SIE does to Mode bits PID Status bits
End Point Mode 3 2 1 0 Token Setup In Out The validity of the received data The quality status of the DMA buffer The number of received bytes Acknowledge phase completed count buffer dval DTOG DVAL COUNT Setup In Out ACK End Point Mode 3 2 1 0 Response Int
Interrupt?
Legend:
UC: unchanged x: don't care
TX: transmit RX: receive
TX0: transmit 0-length packet
available for Control endpoint only
The response of the SIE can be summarized as follows: 1. the SIE will only respond to valid transactions, and will ignore non-valid ones; 2. the SIE will generate IRQ when a valid transaction is completed or when the DMA buffer is corrupted 3. an incoming Data packet is valid if the count is <= 10 (CRC inclusive) and passes all error checking; 4. a Setup will be ignored by all non-Control endpoints (in appropriate modes); 5. an In will be ignored by an Out configured endpoint and vice versa. The In and Out PID status is updated at the end of a transaction.
The Setup PID status is updated at the beginning of the Data packet phase. The entire EndPoint 0 mode and the Count register are locked to CPU writes at the end of any transaction in which an ACK is transferred. These registers are only unlocked upon a CPU read of these registers, and only if that read happens after the transaction completes. This represents about a 1-s window to which to the CPU is locked from register writes to these USB registers. Normally the firmware does a register read at the beginning of the ISR to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction.
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Table 16-2. Details of Modes for Differing Traffic Conditions End Point Mode
3 2 1 0 token count buffer dval DTOG DVAL COUNT
PID
Setup In Out ACK
Set End Point Mode
3 2 1 0 response int
Setup Packet (if accepting)
See Table 16-1 See Table 16-1 See Table 16-1 Disabled 0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange ignore no Setup Setup Setup <= 10 > 10 x data junk junk valid x invalid updates updates updates 1 updates 0 updates updates updates 1 1 1 UC UC UC UC UC UC 1 UC UC 0 0 0 1 ACK ignore ignore yes yes yes NoChange NoChange
Nak In/Out 0 0 0 0 0 0 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 1 UC UC UC NoChange NoChange NAK NAK yes yes
Ignore In/Out 0 0 1 1 0 0 0 0 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC UC UC UC UC UC NoChange NoChange ignore ignore no no
Stall In/Out 0 0 0 0 1 1 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 1 UC UC UC NoChange NoChange Stall Stall yes yes
Control Write
Normal Out/premature status In 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 Out Out Out In <= 10 > 10 x x data junk junk UC valid x invalid x updates updates updates UC 1 updates 0 UC updates updates updates UC UC UC UC UC UC UC UC 1 1 1 1 UC 1 UC UC 1 1 0 1 0 ACK ignore ignore TX 0 yes yes yes yes
NoChange NoChange NoChange
NAK Out/premature status In 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Out Out Out In <= 10 > 10 x x UC UC UC UC valid x invalid x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 UC UC UC UC UC UC 1 NoChange NoChange NoChange NoChange NAK ignore ignore TX 0 yes no no yes
Status In/extra Out 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Out Out Out In <= 10 > 10 x x UC UC UC UC valid x invalid x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 UC UC UC UC UC UC 1 0 0 1 1 Stall ignore ignore TX 0 yes no no yes
NoChange NoChange NoChange
Control Read
Normal In/premature status Out 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Out Out Out Out Out In 2 2 !=2 > 10 x x UC UC UC UC UC UC valid valid valid x invalid x 1 0 updates UC UC UC 1 1 1 UC UC UC updates updates updates UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 1 1 UC UC UC 1 UC UC UC UC 1 NoChange 0 0 ACK yes yes yes no no yes
0 1 1 Stall 0 1 1 Stall ignore ignore
NoChange NoChange 1
1 1 0 ACK (back)
Nak In/premature status Out 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Out Out Out Out Out In 2 2 !=2 > 10 x x UC UC UC UC UC UC valid valid valid x invalid x 1 0 updates UC UC UC 1 1 1 UC UC UC updates updates updates UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 1 1 UC UC UC 1 UC UC UC UC UC NoChange 0 0 ACK yes yes yes no no yes
0 1 1 Stall 0 1 1 Stall ignore ignore NAK
NoChange NoChange NoChange
Status Out/extra In 0 0 0 0 1 1 0 0 Out Out 2 2 UC UC valid valid 1 0 1 1 updates updates UC UC UC UC 1 1 1 UC NoChange 0 ACK yes yes
0 1 1 Stall
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Table 16-2. Details of Modes for Differing Traffic Conditions (continued) End Point Mode
3 0 0 0 0 2 0 0 0 0 1 1 1 1 1 0 0 0 0 0 token Out Out Out In count !=2 > 10 x x buffer UC UC UC UC dval valid x invalid x DTOG updates UC UC UC DVAL 1 UC UC UC COUNT updates UC UC UC
PID
Setup UC UC UC UC In UC UC UC 1 Out 1 UC UC UC ACK UC UC UC UC
Set End Point Mode
3 0 U C U C 0 2 1 0 response 0 1 1 Stall UUU C C C ignore UUU C C C ignore 0 1 1 Stall int yes no no yes
Out endpoint
Normal Out/erroneous In 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Out Out Out In <= 10 > 10 x x data junk junk UC valid x invalid x updates updates updates UC 1 updates 0 UC updates updates updates UC UC UC UC UC UC UC UC UC 1 1 1 UC 1 UC UC UC 1 0 0 0 ACK ignore ignore ignore yes yes yes no
NoChange NoChange NoChange
NAK Out/erroneous In 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Out Out Out In <= 10 > 10 x x UC UC UC UC valid x invalid x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC UC UC UC UC NoChange NoChange NoChange NoChange NAK ignore ignore ignore yes no no no
Isochronous endpoint (Out) 0 0 1 1 0 0 1 1 Out In x x updates UC updates x updates UC updates UC updates UC UC UC UC UC 1 UC 1 UC NoChange NoChange RX ignore yes no
In endpoint
Normal In/erroneous Out 1 1 1 1 0 0 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 UC UC UC 1 NoChange 1 ignore no yes
1 0 0 ACK (back)
NAK In/erroneous Out 1 1 1 1 0 0 0 0 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 UC UC UC UC NoChange NoChange ignore NAK no yes
Isochronous endpoint (In) 0 0 1 1 1 1 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 UC UC UC UC NoChange NoChange ignore TX no yes
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17.0 Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................-65C to +150C Ambient Temperature with Power Applied ...............................................................................................................-0C to +70C Supply Voltage on VCC relative to VSS .................................................................................................................... -0.5V to +7.0V DC Input Voltage........................................................................................................................................... -0.5V to +VCC+0.5V DC Voltage Applied to Outputs in High Z State ........................................................................................... -0.5V to + VCC+0.5V Max. Output Current into Port 0,1,2,3 and DAC[1:0] Pins.................................................................................................... 60 mA Max. Output Current into DAC[7:2] Pins ............................................................................................................................. 10 mA Power Dissipation ..............................................................................................................................................................300 mW Static Discharge Voltage .................................................................................................................................................. > 2000V Latch-up Current ........................................................................................................................................................... > 200 mA
18.0
DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70C
Parameter General Min. 4.0 4.35 Max. 5.5 5.25 40 15 30 -0.4 128 1.024 8.192 0.4 256 128 1.024 14.33 1 60 0.001 2.8 0.2 0.8 0.8 -10 7.35K 1.425 14.25 4.9K 45% 6% 7.2 2.5 2.0 20 10 7.65 1.575 15.75 9.1K 65% 12% 16.5 200 3.6 0.3 Unit V V mA mA A V s s ms ms A mA ms V V V V V pF A k k k Ohms VCC VCC mA All ports, LOW to HIGH edge All ports, HIGH to LOW edge Port 3, Vout = 1.0V (note 1) 0 V < Vin<3.3 V 7.5 k 2% to VCC 1.5 k 5% to 3.0-3.6V 15 k 5% |(D+)-(D-)| 9-1 Any pin Cumulative across all ports (note 8) Linear ramp: 0 to 4.35V (notes 4,5) 15k 5% ohms to Gnd (note 2) Vcc = 5.0V, ceramic resonator Oscillator off, D- > Voh min Conditions Non USB activity (note 1) USB activity (note 2) VCC = 5.5V
VCC (1) VCC (2) ICC1 ICC2 ISB1 VPP Tstart tint1 tint2 twatch Iil Ism tvccs Voh Vol Vdi Vcm Vse Cin Ilo Rpu Rpu Rpd Rup Vith VH Iol
Operating Voltage Operating Voltage VCC Operating Supply Current VCC = 4.35V Supply Current - Suspend Mode Programming Voltage (disabled) Resonator Start-up Interval Internal Timer #1 Interrupt Period Internal Timer #2 Interrupt Period Watch Dog Timer Period Input Leakage Current Max ISS IO Sink Current Power-On Reset VCC Reset Slew USB Interface Static Output HIGH Static Output LOW Differential Input Sensitivity Differential Input Common Mode Range Single-Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage Bus Pull-up Resistance (VCC option) Bus Pull-up Resistance (Ext. 3.3V option) Bus Pull-down Resistance General Purpose I/O Interface Pull-up Resistance Input Threshold Voltage Input Hysteresis Voltage Sink Current
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18.0
Iol Ioh Rup Isink0(0) Isink0(F) Isink1(0) Isink1(F) Irange Ilin tsink Tratio
DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70C (continued)
Parameter Sink Current Source Current DAC Interface Pull-up Resistance DAC[7:2] Sink Current (0) DAC[7:2] Sink Current (F) DAC[1:0] Sink Current (0) DAC[1:0] Sink Current (F) Programmed Isink Ratio: max/min Differential Nonlinearity Current Sink Response Time Tracking Ratio DAC[1:0] to DAC[7:2] 14 8.0K 0.1 0.5 1.6 8 4 20.0K 0.3 1.5 4.8 24 6 0.5 0.8 21 lsb s Ohms mA mA mA mA (note 11) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (notes 2,9) Any pin (note 6) Full scale transition Vout = 2.0V (note 7) Min. 3.5 1.4 Max. 10.6 7.5 Unit mA mA Conditions Port 0,1,2, Vout = 2.0V (note 1) Voh = 2.4V (all ports 0,1,2,3) (note 1)
19.0
Switching Characteristics
Description Clock Input Clock Cycle Time Clock HIGH Time Clock LOW Time USB Driver Characteristics Transition Rise Time Transition Rise Time Transition Fall Time Transition Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage USB Data Timing Low Speed Data Rate Receiver Data Jitter Tolerance Receiver Data Jitter Tolerance Differential to EOP Transition Skew EOP Width at Receiver EOP Width at Receiver Source EOP Width Differential Driver Jitter Differential Driver Jitter 80 1.3 1.4775 -75 -45 -40 330 675 1.25 -95 -150 1.50 95 150 75 300 125 2.0 1.5225 75 45 100 Min. 165.0 0.45 tCYC 0.45 tCYC 75 300 Max. 168.3 Unit ns ns ns ns ns ns ns % V Mbs ns ns ns ns ns s ns ns To next transition, Figure 19-5 To paired transition, Figure 19-5 CLoad = 50 pF [2, 3] CLoad = 600 pF [2, 3] CLoad = 50 pF [2, 3] CLoad = 600 pF [2, 3] tr/tf [2, 3]
[2, 3]
Parameter tCYC tCH tCL tr tr tf tf trfm Vcrs tdrate tdjr1 tdjr2 tdeop teopr1 teopr2 teopt tudj1 tudj2
Conditions
Ave. Bit Rate (1.5 Mb/s 1.5%) To Next Transition [10] For Paired Transitions [10]
[8]
Rejects as EOP [10] Accepts as EOP [10]
Notes: 1. Functionality is guaranteed of the VCC (1) range, except USB transmitter and DACs. 2. USB transmitter functionality is guaranteed over the VCC (2) range, as well as DAC outputs. 3. Per Table 7-7 of revision 1.1 of USB specification, for CLOAD of 50-600 pF. 4. Port 3 bit 7 controls whether the parts goes into suspend after a POR event or waits 128 ms to begin running. 5. POR will re-occur whenever VCC drops to approximately 2.5V. 6. Measured as largest step size vs. nominal according to measured full scale and zero programmed values. 7. Tratio = Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed. 8. Total current cumulative across all Port pins flowing to VSS is limited to minimize Ground-Drop noise effects. 9. Irange: Isinkn(15)/ Isinkn(0) for the same pin. 10. Measured at crossover point of differential data signals. 11. Limits total bus capacitance loading (C LOAD) to 400 pF per section 7.1.5 of revision 1.1 of USB specification.
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.
tCYC tCH
CLOCK
tCL Figure 19-1. Clock Timing
Voh Vcrs Vol
D+
tr
90% 10% 90%
tf
10%
D-
Figure 19-2. USB Data Signal Timing
TPERIOD Differential Data Lines
TJR TJR1 TJR2
Consecutive Transitions N * TPERIOD + TJR1 Paired Transitions N * TPERIOD + TJR2
Figure 19-3. Receiver Jitter Tolerance
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TPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data to SE0 Skew N * TPERIOD + TDEOP
Source EOP Width:
TEOPT
Receiver EOP Width: TEOPR1, TEOPR2
Figure 19-4. Differential to EOP Transition Skew and EOP Width
TPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2
Figure 19-5. Differential Data Jitter
20.0
Ordering Information
Ordering Code EPROM Size 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8KB Package Name P17 O48 O48 P2 SP48 SP48 XW Package Type 40-Pin (600-Mil) PDIP 48-Lead Shrunk Small Outline Package 48-Lead Shrunk Small Outline Package 40-Pin (600-Mil) PDIP Lead-free 48-Lead Shrunk Small Outline Package 48-Lead SSOP Lead-Free Die Lead-Free Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial
CY7C63413-PC CY7C63413-PVC CY7C63513-PVC CY7C63413-PXC CY7C63413-PVXC CY7C63513-PVXC CY7C63413-XWC
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21.0 Die Pad Locations
Table 21-1. DIe Pad Locations (in microns)
Pad #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
D+ DPort3[7] Port3[5] Port3[3] Port3[1] Port2[7] Port2[5] Port2[3] Port2[1] Por1[7] Por1[5] Por1[3] Por1[1] DAC7 DAC5 Port0[7] Port0[5] Port0[3] Port0[1] DAC3 DAC1 VPP VSS
X
1496.95 467.40 345.15 242.15 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 98.00 306.30 442.15 593.40 696.40 824.25 949.65
Y
2995.00 2995.00 3023.60 3023.60 2661.25 2558.25 2455.25 2352.25 2249.25 2146.25 1134.25 1031.25 928.25 825.25 721.05 618.05 516.25 413.25 98.00 98.00 98.00 98.00 98.00 98.00
Pad #
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Pin Name
VCC VSS Port3[6] Port3[4] Port3[2] Port3[0] Port2[6] Port2[4] Port2[2] Port2[0] Port1[6] Port1[4] Port1[2] Port1[0] DAC6 DAC4 Port0[6] Port0[4] Port0[2] Port0[0] DAC2 DAC0 XtalOut XtalIn
X
1619.65 1719.65 1823.10 1926.10 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 2066.30 1858.00 1718.30 1618.50 1513.50 1301.90 1160.50
Y
3023.60 3023.60 3023.60 3023.60 2657.35 2554.35 2451.35 2348.35 2245.35 2142.35 1130.35 1027.35 924.35 821.35 719.55 616.55 512.35 409.35 98.00 98.00 98.00 98.00 98.00 98.00
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22.0 Package Diagrams
48-Lead Shrunk Small Outline Package O48
51-85061-*C
40-Lead (600-Mil) Molded DIP P17
51-85019-A
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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23.0 Document History Page
Document Title: CY7C63413, CY7C63513 Low-speed High I/O, 1.5 -Mbps USB Controller Document Number: 38-08027 REV. ** *A ECN NO. 116224 237148 Issue Date 06/12/02 SEE ECN Orig. of Change DSG KKU Description of Change Change from Spec number: 38-00754 to 38-08027 Removed 24 pin package, CY7C63411/12, CY7C63511/12 and CY7C636XX parts Added Lead-Free part numbers to section 20.0 Added USB Logo.
Document #: 38-08027 Rev. *A
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